Re: [Vala] volatile variable



On Tue, 2014-06-17 at 08:20 +0200, Jürg Billeter wrote:
On Tue, 2014-06-17 at 01:38 +0200, Maciej Piechotka wrote:
On Mon, 2014-06-16 at 10:55 +0800, Nor Jaidi Tuah wrote:
Summary: byte access (read/write) is atomic on
MOST architectures. Dang! I thought ALL.


I'm not sure but there is no guarantee that it is - you don't know it it
will be, say, in ARMv9. Alpha, while probably not in the top 3 most
popular ISA on the world, is a strange architecture.

I'm not aware of any modern CPU where aligned loads or stores (up to
machine word size) are not atomic. While Alpha has no ordering
guarantees, aligned loads and stores are still atomic, as far as I know.
I don't see this changing in the foreseeable future for general purpose
CPUs. You still have to be very careful about reordering issues, though.

Regards,
Jürg


Thanks for clarification. As I wrote I wasn't 100% sure about Alpha, and
I don't have one around to play with it ;)

Best regards

Attachment: signature.asc
Description: This is a digitally signed message part



[Date Prev][Date Next]   [Thread Prev][Thread Next]   [Thread Index] [Date Index] [Author Index]