Saluton,
I'm still using the filter
mailing list contains "@ximian.com"
move to Folder "ximian" in "Local Folders"
and, until now, the only message that was not moved to the ximian folder
is the one attached. Hope that this will help to shed some light. If,
for instance, I send an email to myself, the message is, wrongly, moved
to the ximian folder.
On Thu, 2003-01-09 at 15:33, Marco Monteiro wrote:
Saluton,
if I create a filter like
mailing list contains "@ximian.com"
move to Folder "ximian" in "Local Folders"
evolution moves every message I receive to the specified folder (even if
they don't come from a mailing list, or don't come from a mailing list
with a address in the domain ximian.com). On the other hand, in a filter
where the '@' is not the first letter in the criterion, everything works
has expected. For example
mailing list contains "evolution ximian com"
move to Folder "evolution" in "Local Folders"
works OK. I think the problem is the initial '@'.
Is this a bug, or I'm doing something wrong? I'm using Evolution 1.2.1.
-- Marco Monteiro <masm acm org>
--- Begin Message ---
- From: Doug Burger <dburger CS UTEXAS EDU>
- To: SIGARCH-MEMBERS ACM ORG
- Subject: SIGARCH-MSG: January 2003 Digest of SIGARCH Messages
- Date: Thu, 9 Jan 2003 08:19:29 -0600
This is the January 2003 Digest of SIGARCH Messages (sigarch-jan03): * Hot Chips 2003 Call for Contributions http://www.hotchips.org Submitted by Allen J. Baum <abaum 3wisemonkeys net> * HPCA-9 Call for Participation http://www.cs.arizona.edu/hpca9 Submitted by Soner Onder <soner mtu edu> --Doug Burger SIGARCH Information Director infodir_SIGARCH acm org * Archive: http://www.cs.wisc.edu/~lists/archive/sigarch-members/maillist.html * Web pages: http://www.cs.wisc.edu/~arch/www/, http://www.acm.org/sigarch/ * To remove yourself from the SIGARCH mailing list: mail listserv acm org with message body: unsubscribe SIGARCH-MEMBERS ----------------------------------------------------------------- Doug Burger Office: 3.432 ACES Assistant Professor Phone: 512-471-9795 Department of Computer Sciences Assistant: 512-471-9442 University of Texas at Austin Fax: 512-232-1413 Taylor Hall 2.124 E-mail: dburger cs utexas edu Austin, TX 78712-1188 USA www.cs.utexas.edu/users/dburger ----------------------------------------------------------------- * Hot Chips 2003 Call for Contributions **************************** Call for Contributions *********** Hot Chips, Stanford University, Palo Alto, California, Aug 17-19, 2003 Since it began in 1989, Hot Chips has been known as one of the semiconductor industry's leading conferences on high-performance microprocessors and related integrated circuits. The conference is held once a year in August on the Stanford University campus in the center of the world's capital of electronics activity, Silicon Valley. The emphasis this year, as in previous years, is on real products and realizable technology. Topics of interest for this year's conference include: - Microprocessors - Systems-on-chip - Embedded processors - Digital signal processors - Application-specific processors - Graphics/Multimedia/Game processors - Communication/networking chips - Wireless LAN/Wireless WAN chips - Network/security processors - Low-power chips - Novel chips: quantum computing, microarray - Reliability and design for test - Performance evaluation - Compiler technology - Operating system/chip interaction - Dynamic power management - Advanced semiconductor process technology - Reconfigurable Processors Presentations at Hot Chips are in the form of 30-minute talks. Presentation slides will be published in the Hot Chips Proceedings. Participants are not required to submit written papers, but a select group will be invited to submit a paper for inclusion in a special issue of IEEE Micro. Submissions must consist of a title, extended abstract (three pages maximum), and the presenter's contact information (name, affiliation, job title, address, phone, fax, and email). Please indicate whether you have submitted or intend to submit a similar or overlapping submission to another conference or journal. Also indicate if you would like the submission to be held confidential until the conference; we do our best to maintain confidentiality. Submissions are evaluated by the Program Committee on the basis of the performance of the device, degree of innovation, use of advanced technology, and potential market significance. Authors will be notified of the status of their submission by the end of April, 2003. Don't miss this chance to present your device to an audience of the leading technologists in the world of semiconductors. Submissions must be received no later than March 15,2003. Please make your submissions in Adobe Acrobat PDF format by email to: hotchips-submission arith stanford edu For more information check out the Hot Chips 15 Web site at: http://www.hotchips.org. Send questions to: hotchips arith stanford edu or contact Prof. Michael Flynn at flynn ee stanford edu, or Pradeep K. Dubey at pdubey broadcom com, or 408-922-5904. ---------------------------------------------------------------------- ---------------------------------------------------------------------- * HPCA-9 Call for Participation *--------------------------------------------------------------------* * CALL FOR PARTICIPATION * * * * ON-LINE REGISTRATION is now OPEN. * * EARLY REGISTRATION DEADLINE: * * 5:00pm Eastern FRIDAY, JANUARY 17, 2003. * * * * Please note: * * Early registration deadline is 8 days away. * * In order to get the conference rate, hotel reservations * * must be made by Jan 17. * * * * NP-2 Workshop has been extended to 1-1/2 days now. * * Network processors tutorial date/time/organizers change. * *--------------------------------------------------------------------* HPCA - 9 Anaheim, California February 8-12, 2003 The International Symposium on High-Performance Computer Architecture provides a high quality forum for scientists and engineers to present their latest research findings in this rapidly changing field. HPCA-9, the ninth in the series of International Symposium on High Performance Computer Architecture, will be held in Anaheim, California. Please visit the conference web page at: http://www.cs.arizona.edu/hpca9 *****============================================================***** * ADVANCE PROGRAM * *****============================================================***** *====================================================================* * Saturday, February 8 * *====================================================================* Workshops (8:00am - 5:00pm) --------------------------- INTERACT-7 The 7th Annual Workshop on Interaction between Compilers and Computer Architecture SAN-2 2nd Annual Workshop on Novel Uses of System Area Networks NP-2 The Second Workshop on Network Processors (Starts 1:30pm) Tutorial (8:30am - 12:30n) --------------------------- An introduction to Network Processors Patrick Crowley, U. Washington Raj Yavatkar, Intel Corporation *====================================================================* * Sunday, February 9 * *====================================================================* Workshops (8:00am - 5:00pm) --------------------------- CAECW Sixth Workshop on Computer Architecture Evaluation using Commercial Workloads NP-2 The Second Workshop on Network Processors SSRS Workshop on Software Support for Reconfigurable Systems Tutorial (Morning) -------------------- New Computing Platforms for Embedded Systems Frank Vahid & Walid Najjar, U. California Riverside Tutorial (Afternoon) -------------------- Simics Microarchitect's Toolset Peter Magnuson, Virtutech *====================================================================* * Monday, February 10 * *====================================================================* ---------------------------------------------------------------------- Welcome (8:45am - 9:00am) ---------------------------------------------------------------------- ---------------------------------------------------------------------- Keynote I (9:00am - 10:00am) Chair : Laxmi Bhuyan ---------------------------------------------------------------------- Billion Transistor Chips in Mainstream Enterprise Platforms of the Future Dileep Bhandarkar Architect-at-large, Enterprise Platforms Group, Intel Corporation ---------------------------------------------------------------------- ---------------------------------------------------------------------- Break (10:00 am - 10:30 am) ---------------------------------------------------------------------- ---------------------------------------------------------------------- Session 1 : Multithreading (10:30am -- 12:00n) Chair: Antonio Gonzalez Variability in Architectural Simulations of Multi-threaded Workloads Alaa Alameldeen and David Wood Mini-threads: Increasing TLP on Small-Scale SMT Processors Joshua Redstone, Susan Eggers, and Henry Levy Front-End Policies for Improved Issue Efficiency in SMT Processors Ali El-Moursy and David Albonesi ---------------------------------------------------------------------- ---------------------------------------------------------------------- Lunch (12:00n - 1:30pm) ---------------------------------------------------------------------- ---------------------------------------------------------------------- Session 2 : Branch Prediction (1:30pm - 3:00pm) Chair: Susan Eggers Reconsidering Complex Branch Predictors Daniel Jimenez Incorporating Predicate Information Into Branch Predictors Beth Simon, Brad Calder, and Jeanne Ferrante Dynamic Data Dependence Tracking and its Application to Branch Prediction Lei Chen, Steve Dropsho, and David Albonesi ---------------------------------------------------------------------- ---------------------------------------------------------------------- Break (3:00pm - 3:30 pm) ---------------------------------------------------------------------- ---------------------------------------------------------------------- Session 3 : Power Efficient Designs (3:30pm - 5:30pm) Chair: Saman Amarasinghe Control Techniques to Eliminate Voltage Emergencies in High-Performance Processors Russ Joseph, David Brooks, and Margaret Martonosi Dynamic Voltage Scaling with Links for Power Optimization of Interconnection Networks Li Shang, Li-Shiuan Peh, and Niraj Jha Power-Aware Control Speculation through Selective Throttling Juan L. Aragon, Jose Gonzalez, and Antonio Gonzalez Deterministic Clock Gating For Microprocessor Power Reduction Hai Li, Swarup Bhunia, Yiran Chen, Kaushik Roy, and T.N. Vijaykumar ---------------------------------------------------------------------- ---------------------------------------------------------------------- BANQUET ---------------------------------------------------------------------- *====================================================================* * Tuesday, February 11 * *====================================================================* ---------------------------------------------------------------------- Keynote II (8:30am - 9:30am) Chair: Brad Calder Beyond Performance: Some (other) Challenges for Future Microprocessors. Eric Kronstadt Director, VLSI Systems, IBM TJ Watson ---------------------------------------------------------------------- ---------------------------------------------------------------------- Break (9:30am - 10:00am) ---------------------------------------------------------------------- ---------------------------------------------------------------------- Session 4 : Superscalars (10:00am - 12:00n) Chair: David Wood Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-order Processors Onur Mutlu, Jared Stark, Chris Wilkerson, and Yale Patt Microarchitecture and Performance Analysis of a SPARC-V9 Microprocessor for Enterprise Server Systems Mariko Sakamoto, Akira Katsuno, Alichiro Inoue, Takeo Asakawa, Haruhiko Ueno, and Kuniki Morita Exploring the VLSI Scalability of Stream Processors Brucek Khailany, William J. Dally, Scott Rixner, Ujval J. Kapasi, John Owens, and Brain Towles Dynamic Optimization Of Micro-Operations Brian Slechta, Brian Fahs, David Crowe, Michael Fertig, Gregory Muthler, Justin Quek Francesco Spadini, Sanjay J. Patel, and Steven S. Lumetta ---------------------------------------------------------------------- ---------------------------------------------------------------------- Luncheon (12:00n - 1:30pm) ---------------------------------------------------------------------- ---------------------------------------------------------------------- Session 5 : Multiprocessor Systems (1:30pm - 3:00pm) Chair: Chita Das Slipstream Execution Mode for CMP-Based Multiprocessors Khaled Ibrahim, Gregory Byrd, and Eric Rotenberg Tradeoffs in Buffering Memory State for Thread-Level Speculation in Multiprocessors Maria Garzaran, Milos Prvulovic, Victor Vinals, Jose Llaberia, Lawrence Rauchwerger, and Josep Torrellas Dynamic Data Replication: An approach to Providing Fault-Tolerant Shared Memory Clusters Rosalia Christodoulopoulou, Reza Azimi, and Angelos Bilas ---------------------------------------------------------------------- ---------------------------------------------------------------------- Break (3:00pm - 3:30pm) ---------------------------------------------------------------------- ---------------------------------------------------------------------- Session 6 : Memory and Communication Performance (3:30pm - 5:30pm) Chair: David Albonesi Memory System Behavior of Java-Based Middleware Martin Karlsson, Kevin Moore, Erik Hagersten, and David Wood Evaluating the Impact of Communication Architecture on the Performability of Cluster-Based Services Kiran Nagaraja, Neeraj Krishnan, Ricardo Bianchini, Richard Martin, and Thu Nguyen Hierarchical Back-Off Lock for Non-Uniform Communication Architectures Zoran Radovic and Erik Hagersten Performance Enhancement Techniques for InfiniBand Architecture Eun Jung Kim, Ki Hwan Yum, Chita Das, Mazin Yousif, and Jose Duato ---------------------------------------------------------------------- *====================================================================* * Wednesday, February 12 * *====================================================================* ---------------------------------------------------------------------- Keynote III (8:00am - 9:00am) Chair: Josep Torrellas The State of State Peter Kogge McCourtney Professor of Computer Science and Engineering, University of Notre Dame ---------------------------------------------------------------------- ---------------------------------------------------------------------- Session 7 : Profiling and Simulation Support (9:00am - 10:00am) Chair: Bill Mangione-Smith Catching Accurate Profiles in Hardware Satish Narayanasamy, Timothy Sherwood, Suleyman Sair, Brad Calder, and George Varghese A Statistically Rigorous Approach for Improving Simulation Methodology Joshua Yi, David Lilja, and Douglas Hawkins ---------------------------------------------------------------------- ---------------------------------------------------------------------- Break (10:00am - 10:30am) ---------------------------------------------------------------------- ---------------------------------------------------------------------- Session 8 (10:30 am - 12:30 pm) 8A - Caching and Prefetching ---------------------------- Chair: Soner Onder Caches and Merkle Trees for Efficient Memory Authentication Blaise Gassend, Ed Suh, Dwaine Clarke, Marten van Dijk, and Srinivas Devadas Just Say No: Benefits of Early Cache Miss Determination Gokhan Memik, Glenn Reinman, and William Mangione-Smith TCP: Tag Correlating Prefetchers Zhigang Hu, Stefanos Kaxiras, and Margaret Martonosi Cost-sensitive Cache Replacement Algorithms Jaeheon Jeong and Michel Dubois 8B - Networks and Communication ------------------------------- Chair: Qing Yang Scalar Operand Networks Michael Taylor, Walter Lee, Saman Amarasinghe, and Anant Agarwal Inter-cluster Communication Models for Clustered VLIW processors Andrei Terechko, Erwan Le Thenaff, Manish Garg, Jos van Eijndhoven, and Henk Corporaal A Methodology for Designing Efficient On-Chip Interconnects on Well-behaved Communication Patterns Wai Hong Ho and Timothy Pinkston Active I/O Switches in System Area Networks Ming Hao and Mark Heinrich *****============================================================***** * End of program * *****============================================================*****
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