[vte/wip/egmont/bidi: 51/83] c++ refactoring
- From: Egmont Koblinger <egmontkob src gnome org>
- To: commits-list gnome org
- Cc:
- Subject: [vte/wip/egmont/bidi: 51/83] c++ refactoring
- Date: Thu, 3 Jan 2019 12:57:41 +0000 (UTC)
commit a79921cd920c0cbd94e83244edb7f63d7230462c
Author: Egmont Koblinger <egmont gmail com>
Date: Wed Aug 29 12:43:26 2018 +0200
c++ refactoring
src/bidi.cc | 228 +++++++++++++++++++++++++++++++++---------------------------
src/bidi.hh | 92 +++++++++++++++---------
src/vte.cc | 31 +++++----
3 files changed, 202 insertions(+), 149 deletions(-)
---
diff --git a/src/bidi.cc b/src/bidi.cc
index de9f9c8a..97360364 100644
--- a/src/bidi.cc
+++ b/src/bidi.cc
@@ -30,6 +30,87 @@
using namespace vte::base;
+BidiRow::BidiRow()
+{
+ m_width_alloc = 128;
+
+ m_log2vis = (vte::grid::column_t *) g_malloc (sizeof (vte::grid::column_t) * m_width_alloc);
+ m_vis2log = (vte::grid::column_t *) g_malloc (sizeof (vte::grid::column_t) * m_width_alloc);
+ m_vis_rtl = (guint8 *) g_malloc (sizeof (guint8) * m_width_alloc);
+}
+
+BidiRow::~BidiRow()
+{
+ g_free (m_log2vis);
+ g_free (m_vis2log);
+ g_free (m_vis_rtl);
+}
+
+void BidiRow::set_width(vte::grid::column_t width)
+{
+ if (G_UNLIKELY (width > m_width_alloc)) {
+ while (width > m_width_alloc) {
+ m_width_alloc *= 2;
+ }
+ m_log2vis = (vte::grid::column_t *) g_realloc (m_log2vis, sizeof (vte::grid::column_t) *
m_width_alloc);
+ m_vis2log = (vte::grid::column_t *) g_realloc (m_vis2log, sizeof (vte::grid::column_t) *
m_width_alloc);
+ m_vis_rtl = (guint8 *) g_realloc (m_vis_rtl, sizeof (guint8) * m_width_alloc);
+ }
+
+ m_width = width;
+}
+
+/* Converts from logical to visual column. Offscreen columns are mirrored
+ * for RTL lines, e.g. (assuming 80 columns) -1 <=> 80, -2 <=> 81 etc. */
+vte::grid::column_t BidiRow::log2vis(vte::grid::column_t col) const
+{
+ if (G_LIKELY (col >= 0 && col < m_width)) {
+ return m_log2vis[col];
+ } else {
+ return m_base_rtl ? m_width - 1 - col : col;
+ }
+}
+
+/* Converts from visual to logical column. Offscreen columns are mirrored
+ * for RTL lines, e.g. (assuming 80 columns) -1 <=> 80, -2 <=> 81 etc. */
+vte::grid::column_t BidiRow::vis2log(vte::grid::column_t col) const
+{
+ if (G_LIKELY (col >= 0 && col < m_width)) {
+ return m_vis2log[col];
+ } else {
+ return m_base_rtl ? m_width - 1 - col : col;
+ }
+}
+
+/* Whether the cell at the given visual position has RTL directionality.
+ * For offscreen columns the line's direction is returned. */
+bool BidiRow::vis_is_rtl(vte::grid::column_t col) const
+{
+ if (G_LIKELY (col >= 0 && col < m_width)) {
+ return m_vis_rtl[col];
+ } else {
+ return m_base_rtl;
+ }
+}
+
+/* Whether the cell at the given logical position has RTL directionality.
+ * For offscreen columns the line's direction is returned. */
+bool BidiRow::log_is_rtl(vte::grid::column_t col) const
+{
+ if (G_LIKELY (col >= 0 && col < m_width)) {
+ col = m_log2vis[col];
+ return m_vis_rtl[col];
+ } else {
+ return m_base_rtl;
+ }
+}
+
+bool BidiRow::base_is_rtl() const
+{
+ return m_base_rtl;
+}
+
+
RingView::RingView()
{
m_ring = nullptr;
@@ -37,50 +118,45 @@ RingView::RingView()
m_start = m_len = m_width = 0;
m_height_alloc = 32;
- m_width_alloc = 128;
- m_bidirows = (bidirow *) g_malloc (sizeof (bidirow) * m_height_alloc);
+ m_bidirows.resize(m_height_alloc);
for (int i = 0; i < m_height_alloc; i++) {
- m_bidirows[i].map = (bidicellmap *) g_malloc (sizeof (bidicellmap) * m_width_alloc);
+ m_bidirows[i] = new BidiRow();
}
}
RingView::~RingView()
{
- for (int i = 0; i < m_height_alloc; i++)
- g_free (m_bidirows[i].map);
- g_free (m_bidirows);
+ for (int i = 0; i < m_height_alloc; i++) {
+ delete m_bidirows[i];
+ }
}
-void RingView::set_ring(Ring *r)
+void RingView::set_ring(Ring *ring)
{
- m_ring = r;
+ m_ring = ring;
}
-void RingView::set_width(long w)
+void RingView::set_width(vte::grid::column_t width)
{
- if (G_UNLIKELY (w > m_width_alloc)) {
- while (w > m_width_alloc) {
- m_width_alloc *= 2;
- }
- for (int i = 0; i < m_height_alloc; i++) {
- m_bidirows[i].map = (bidicellmap *) g_realloc (m_bidirows[i].map, sizeof
(bidicellmap) * m_width_alloc);
- }
+ for (int i = 0; i < m_height_alloc; i++) {
+ m_bidirows[i]->set_width(width);
}
- m_width = w;
+ m_width = width;
}
-void RingView::set_rows(long s, long l)
+void RingView::set_rows(vte::grid::row_t s, vte::grid::row_t l)
{
if (G_UNLIKELY (l > m_height_alloc)) {
int i = m_height_alloc;
while (l > m_height_alloc) {
m_height_alloc *= 2;
}
- m_bidirows = (bidirow *) g_realloc (m_bidirows, sizeof (bidirow) * m_height_alloc);
+ m_bidirows.resize(m_height_alloc);
for (; i < m_height_alloc; i++) {
- m_bidirows[i].map = (bidicellmap *) g_malloc (sizeof (bidicellmap) * m_width_alloc);
+ m_bidirows[i] = new BidiRow();
+ m_bidirows[i]->set_width(m_width);
}
}
@@ -90,7 +166,7 @@ void RingView::set_rows(long s, long l)
void RingView::update()
{
- long i = m_start;
+ vte::grid::row_t i = m_start;
const VteRowData *row_data = m_ring->index(m_start);
if (row_data->attr.bidi_flags & VTE_BIDI_IMPLICIT) {
@@ -104,91 +180,40 @@ void RingView::update()
}
}
-bidicellmap *RingView::get_row_map(long row) // FIXME remove this?
+BidiRow const* RingView::get_row_map(vte::grid::row_t row) const
{
g_assert_cmpint (row, >=, m_start);
g_assert_cmpint (row, <, m_start + m_len);
- return m_bidirows[row - m_start].map;
+ return m_bidirows[row - m_start];
}
-/* Converts from logical to visual column. Offscreen columns are mirrored
- * for RTL lines, e.g. (assuming 80 columns) -1 <=> 80, -2 <=> 81 etc. */
-long RingView::log2vis(long row, long col)
+BidiRow* RingView::get_row_map_writable(vte::grid::row_t row)
{
g_assert_cmpint (row, >=, m_start);
g_assert_cmpint (row, <, m_start + m_len);
- bidirow *brow = &m_bidirows[row - m_start];
- if (G_LIKELY (col >= 0 && col < m_width)) {
- return brow->map[col].log2vis;
- } else {
- return brow->rtl ? m_width - 1 - col : col;
- }
-}
-
-/* Converts from visual to logical column. Offscreen columns are mirrored
- * for RTL lines, e.g. (assuming 80 columns) -1 <=> 80, -2 <=> 81 etc. */
-long RingView::vis2log(long row, long col)
-{
- g_assert_cmpint (row, >=, m_start);
- g_assert_cmpint (row, <, m_start + m_len);
- bidirow *brow = &m_bidirows[row - m_start];
- if (G_LIKELY (col >= 0 && col < m_width)) {
- return brow->map[col].vis2log;
- } else {
- return brow->rtl ? m_width - 1 - col : col;
- }
-}
-
-/* Whether the cell at the given visual position has RTL directionality.
- * For offscreen columns the line's direction is returned. */
-bool RingView::vis_is_rtl(long row, long col)
-{
- g_assert_cmpint (row, >=, m_start);
- g_assert_cmpint (row, <, m_start + m_len);
- bidirow *brow = &m_bidirows[row - m_start];
- if (G_LIKELY (col >= 0 && col < m_width)) {
- return brow->map[col].vis_rtl;
- } else {
- return brow->rtl;
- }
-}
-
-/* Whether the cell at the given logical position has RTL directionality.
- * For offscreen columns the line's direction is returned. */
-bool RingView::log_is_rtl(long row, long col)
-{
- g_assert_cmpint (row, >=, m_start);
- g_assert_cmpint (row, <, m_start + m_len);
- bidirow *brow = &m_bidirows[row - m_start];
- if (G_LIKELY (col >= 0 && col < m_width)) {
- col = brow->map[col].log2vis;
- return brow->map[col].vis_rtl;
- } else {
- return brow->rtl;
- }
+ return m_bidirows[row - m_start];
}
/* Set up the mapping according to explicit mode for a given line. */
-void RingView::explicit_line(long row, bool rtl)
+void RingView::explicit_line(vte::grid::row_t row, bool rtl)
{
int i;
- bidicellmap *map;
if (G_UNLIKELY (row < m_start || row >= m_start + m_len))
return;
- m_bidirows[row - m_start].rtl = rtl;
- map = m_bidirows[row - m_start].map;
+ BidiRow *bidirow = get_row_map_writable(row);
+ bidirow->m_base_rtl = rtl;
if (G_UNLIKELY (rtl)) {
for (i = 0; i < m_width; i++) {
- map[i].log2vis = map[i].vis2log = m_width - 1 - i;
- map[i].vis_rtl = TRUE;
+ bidirow->m_log2vis[i] = bidirow->m_vis2log[i] = m_width - 1 - i;
+ bidirow->m_vis_rtl[i] = TRUE;
}
} else {
for (i = 0; i < m_width; i++) {
- map[i].log2vis = map[i].vis2log = i;
- map[i].vis_rtl = FALSE;
+ bidirow->m_log2vis[i] = bidirow->m_vis2log[i] = i;
+ bidirow->m_vis_rtl[i] = FALSE;
}
}
}
@@ -196,7 +221,7 @@ void RingView::explicit_line(long row, bool rtl)
/* Set up the mapping according to explicit mode, for all the lines
* of a paragraph beginning at the given line.
* Returns the row number after the paragraph or viewport (whichever ends first). */
-long RingView::explicit_paragraph(long row, bool rtl)
+vte::grid::row_t RingView::explicit_paragraph(vte::grid::row_t row, bool rtl)
{
const VteRowData *row_data;
@@ -214,9 +239,9 @@ long RingView::explicit_paragraph(long row, bool rtl)
* Returns -1 if have to walk backwards too much. */
/* FIXME this could be much cheaper, we don't need to read the actual rows (text_stream),
* we only need the soft_wrapped flag which is stored in row_stream. Needs method in ring. */
-long RingView::find_paragraph(long row)
+vte::grid::row_t RingView::find_paragraph(vte::grid::row_t row)
{
- long row_stop = row - VTE_BIDI_PARAGRAPH_LENGTH_MAX;
+ vte::grid::row_t row_stop = row - VTE_BIDI_PARAGRAPH_LENGTH_MAX;
const VteRowData *row_data;
while (row-- > row_stop) {
@@ -231,7 +256,7 @@ long RingView::find_paragraph(long row)
/* Figure out the mapping for the paragraph starting at the given row.
* Returns the row number after the paragraph or viewport (whichever ends first). */
-long RingView::paragraph(long row)
+vte::grid::row_t RingView::paragraph(vte::grid::row_t row)
{
const VteRowData *row_data;
@@ -241,7 +266,7 @@ long RingView::paragraph(long row)
bool autodir;
FriBidiParType pbase_dir;
FriBidiLevel level;
- bidicellmap *map;
+ BidiRow *bidirow;
#endif /* WITH_FRIBIDI */
row_data = m_ring->index(row);
@@ -354,8 +379,8 @@ long RingView::paragraph(long row)
row = m_start;
}
while (row < m_start + m_len) {
- m_bidirows[row - m_start].rtl = rtl;
- map = m_bidirows[row - m_start].map;
+ bidirow = get_row_map_writable(row);
+ bidirow->m_base_rtl = rtl;
row_data = m_ring->index(row);
if (row_data == nullptr)
@@ -406,8 +431,8 @@ long RingView::paragraph(long row)
/* Unused cells on the left for RTL paragraphs */
int unused = MAX(m_width - row_data->len, 0);
for (; tv < unused; tv++) {
- map[tv].vis2log = m_width - 1 - tv;
- map[tv].vis_rtl = TRUE;
+ bidirow->m_vis2log[tv] = m_width - 1 - tv;
+ bidirow->m_vis_rtl[tv] = TRUE;
}
}
for (fv = lines[line]; fv < lines[line + 1]; fv++) {
@@ -420,16 +445,16 @@ long RingView::paragraph(long row)
if (FRIBIDI_LEVEL_IS_RTL(fribidi_levels[fl])) {
/* RTL character directionality. Map fragments in reverse order. */
for (col = 0; col < cell->attr.columns(); col++) {
- map[tv + col].vis2log = tl + cell->attr.columns() - 1 - col;
- map[tv + col].vis_rtl = TRUE;
+ bidirow->m_vis2log[tv + col] = tl + cell->attr.columns() - 1 - col;
+ bidirow->m_vis_rtl[tv + col] = TRUE;
}
tv += cell->attr.columns();
tl += cell->attr.columns();
} else {
/* LTR character directionality. */
for (col = 0; col < cell->attr.columns(); col++) {
- map[tv].vis2log = tl;
- map[tv].vis_rtl = FALSE;
+ bidirow->m_vis2log[tv] = tl;
+ bidirow->m_vis_rtl[tv] = FALSE;
tv++;
tl++;
}
@@ -439,8 +464,8 @@ long RingView::paragraph(long row)
/* Unused cells on the right for LTR paragraphs */
g_assert_cmpint (tv, ==, MIN (row_data->len, m_width));
for (; tv < m_width; tv++) {
- map[tv].vis2log = tv;
- map[tv].vis_rtl = FALSE;
+ bidirow->m_vis2log[tv] = tv;
+ bidirow->m_vis_rtl[tv] = FALSE;
}
}
g_assert_cmpint (tv, ==, m_width);
@@ -449,17 +474,17 @@ long RingView::paragraph(long row)
* In debug mode assert that we have a bijective mapping. */
if (_vte_debug_on (VTE_DEBUG_BIDI)) {
for (tl = 0; tl < m_width; tl++) {
- map[tl].log2vis = -1;
+ bidirow->m_log2vis[tl] = -1;
}
}
for (tv = 0; tv < m_width; tv++) {
- map[map[tv].vis2log].log2vis = tv;
+ bidirow->m_log2vis[bidirow->m_vis2log[tv]] = tv;
}
if (_vte_debug_on (VTE_DEBUG_BIDI)) {
for (tl = 0; tl < m_width; tl++) {
- g_assert_cmpint (map[tl].log2vis, !=, -1);
+ g_assert_cmpint (bidirow->m_log2vis[tl], !=, -1);
}
}
@@ -476,6 +501,7 @@ next_line:
#endif /* !WITH_FRIBIDI */
}
+
gboolean vte_bidi_get_mirror_char (gunichar ch, gboolean mirror_box_drawing, gunichar *mirrored_ch)
{
static const unsigned char mirrored_2500[0x80] = {
diff --git a/src/bidi.hh b/src/bidi.hh
index 46a73bf4..4685d9ca 100644
--- a/src/bidi.hh
+++ b/src/bidi.hh
@@ -19,66 +19,92 @@
#pragma once
#include <glib.h>
+#include <vector>
#include "ring.hh"
#include "vterowdata.hh"
+#include "vtetypes.hh"
-// FIXME these names are ugly. Also, make these declarations private if possible.
-struct _bidicellmap {
- int log2vis;
- int vis2log;
- guint8 vis_rtl: 1;
-};
+namespace vte {
-typedef struct _bidicellmap bidicellmap;
+namespace base { // FIXME ???
-struct _bidirow {
- guint8 rtl: 1;
- bidicellmap *map;
-};
+/* BidiRow contains the BiDi transformation of a single row. */
+class BidiRow {
+ friend class RingView;
-typedef struct _bidirow bidirow;
+public:
+ BidiRow();
+ ~BidiRow();
+
+ // prevent accidents
+ BidiRow(BidiRow& o) = delete;
+ BidiRow(BidiRow const& o) = delete;
+ BidiRow(BidiRow&& o) = delete;
+ BidiRow& operator= (BidiRow& o) = delete;
+ BidiRow& operator= (BidiRow const& o) = delete;
+ BidiRow& operator= (BidiRow&& o) = delete;
+
+ vte::grid::column_t log2vis(vte::grid::column_t col) const;
+ vte::grid::column_t vis2log(vte::grid::column_t col) const;
+ bool log_is_rtl(vte::grid::column_t col) const;
+ bool vis_is_rtl(vte::grid::column_t col) const;
+ bool base_is_rtl() const;
-namespace vte {
+private:
+ void set_width(vte::grid::column_t width);
-namespace base { // FIXME ???
+ vte::grid::column_t m_width;
+ vte::grid::column_t m_width_alloc;
+ vte::grid::column_t *m_log2vis;
+ vte::grid::column_t *m_vis2log;
+ guint8 *m_vis_rtl;
+
+ guint8 m_base_rtl: 1;
+};
+
+
+/* RingView contains the BiDi transformations for all the rows of the viewport. */
class RingView {
public:
RingView();
~RingView();
+ // prevent accidents
+ RingView(RingView& o) = delete;
+ RingView(RingView const& o) = delete;
+ RingView(RingView&& o) = delete;
+ RingView& operator= (RingView& o) = delete;
+ RingView& operator= (RingView const& o) = delete;
+ RingView& operator= (RingView&& o) = delete;
+
void set_ring(Ring *ring);
- void set_rows(long start, long len);
- void set_width(long width);
+ void set_rows(vte::grid::row_t start, vte::grid::row_t len);
+ void set_width(vte::grid::column_t width);
void update();
- bidicellmap *get_row_map(long row); // FIXME remove?
-
- long log2vis(long row, long col);
- long vis2log(long row, long col);
- bool log_is_rtl(long row, long col);
- bool vis_is_rtl(long row, long col);
+ BidiRow const* get_row_map(vte::grid::row_t row) const;
private:
Ring *m_ring;
- bidirow *m_bidirows;
+ std::vector<BidiRow *> m_bidirows;
- long m_start;
- long m_len;
- long m_width;
+ vte::grid::row_t m_start;
+ vte::grid::row_t m_len;
+ vte::grid::column_t m_width;
- long m_height_alloc;
- long m_width_alloc;
+ vte::grid::row_t m_height_alloc;
- void explicit_line(long row, bool rtl);
- long explicit_paragraph(long row, bool rtl);
- long find_paragraph(long row);
- long paragraph(long row);
-};
+ BidiRow* get_row_map_writable(vte::grid::row_t row);
+ void explicit_line(vte::grid::row_t row, bool rtl);
+ vte::grid::row_t explicit_paragraph(vte::grid::row_t row, bool rtl);
+ vte::grid::row_t find_paragraph(vte::grid::row_t row);
+ vte::grid::row_t paragraph(vte::grid::row_t row);
+};
}; /* namespace base */
diff --git a/src/vte.cc b/src/vte.cc
index 640b41f5..f36c29b1 100644
--- a/src/vte.cc
+++ b/src/vte.cc
@@ -8839,7 +8839,7 @@ Terminal::draw_cells_with_attributes(struct _vte_draw_text_request *items,
/* XXX tmp hack */
#define _vte_row_data_get_visual(row_data_p, bidimap, col) \
- _vte_row_data_get(row_data_p, bidimap[col].vis2log)
+ row_data_p == nullptr ? nullptr : _vte_row_data_get(row_data_p, bidimap->vis2log(col))
/* Paint the contents of a given row at the given location. Take advantage
@@ -8865,7 +8865,7 @@ Terminal::draw_rows(VteScreen *screen_,
guint item_count;
const VteCell *cell;
VteRowData const* row_data;
- bidicellmap const* bidimap;
+ vte::base::BidiRow const* bidirow;
auto const column_count = m_column_count;
uint32_t const attr_mask = m_allow_bold ? ~0 : ~VTE_ATTR_BOLD_MASK;
@@ -8890,27 +8890,27 @@ Terminal::draw_rows(VteScreen *screen_,
* Process each row independently. */
for (row = start_row, y = start_y; row < end_row; row++, y += row_height) {
row_data = find_row_data(row);
- bidimap = m_ringview.get_row_map(row);
+ bidirow = m_ringview.get_row_map(row);
i = j = 0;
/* Walk the line.
* Locate runs of identical bg colors within a row, and paint each run as a single
rectangle. */
do {
/* Get the first cell's contents. */
- cell = row_data ? _vte_row_data_get_visual (row_data, bidimap, i) : nullptr;
+ cell = row_data ? _vte_row_data_get_visual (row_data, bidirow, i) : nullptr;
/* Find the colors for this cell. */
selected = cell_is_selected(i, row);
determine_colors(cell, selected, &fore, &back, &deco);
- rtl = bidimap[i].vis_rtl;
+ rtl = bidirow->vis_is_rtl(i);
while (++j < column_count) {
/* Retrieve the next cell. */
- cell = row_data ? _vte_row_data_get_visual (row_data, bidimap, j) : nullptr;
+ cell = row_data ? _vte_row_data_get_visual (row_data, bidirow, j) : nullptr;
/* Resolve attributes to colors where possible and
* compare visual attributes to the first character
* in this chunk. */
selected = cell_is_selected(j, row);
determine_colors(cell, selected, &nfore, &nback, &ndeco);
- nrtl = bidimap[j].vis_rtl;
+ nrtl = bidirow->vis_is_rtl(j);
if (nback != back || (_vte_debug_on (VTE_DEBUG_BIDI) && nrtl != rtl)) {
break;
}
@@ -8954,14 +8954,14 @@ Terminal::draw_rows(VteScreen *screen_,
/* Skip row. */
continue;
}
- bidimap = m_ringview.get_row_map(row);
+ bidirow = m_ringview.get_row_map(row);
/* Walk the line.
* Locate runs of identical attributes within a row, and draw each run using a single
draw_cells() call. */
item_count = 0;
for (col = 0; col < column_count; col++) {
/* Get the character cell's contents. */
- cell = _vte_row_data_get_visual (row_data, bidimap, col);
+ cell = _vte_row_data_get_visual (row_data, bidirow, col);
if (cell == NULL) {
/* We're rendering BiDi text in visual order, so an unused cell can be
followed by a used one. */
continue;
@@ -9021,9 +9021,9 @@ Terminal::draw_rows(VteScreen *screen_,
g_assert_cmpint (item_count, <, column_count);
items[item_count].c = cell->c;
items[item_count].columns = cell->attr.columns();
- items[item_count].x = (col - (bidimap[i].vis_rtl ? cell->attr.columns() - 1 : 0)) *
column_width;
+ items[item_count].x = (col - (bidirow->vis_is_rtl(col) ? cell->attr.columns() - 1 :
0)) * column_width;
items[item_count].y = y;
- items[item_count].mirror = bidimap[i].vis_rtl;
+ items[item_count].mirror = bidirow->vis_is_rtl(col);
items[item_count].box_mirror = !!(row_data->attr.bidi_flags & VTE_BIDI_BOX_MIRROR);
item_count++;
}
@@ -9160,6 +9160,7 @@ Terminal::paint_cursor()
/* Find the first cell of the character "under" the cursor.
* This is for CJK. For TAB, paint the cursor where it really is. */
VteRowData const *row_data = find_row_data(drow);
+ vte::base::BidiRow const *bidirow = m_ringview.get_row_map(drow);
auto cell = find_charcell(col, drow);
while (cell != NULL && cell->attr.fragment() && cell->c != '\t' && col > 0) {
@@ -9168,12 +9169,12 @@ Terminal::paint_cursor()
}
/* Draw the cursor. */
- viscol = m_ringview.log2vis(drow, col);
+ viscol = bidirow->log2vis(col);
item.c = (cell && cell->c) ? cell->c : ' ';
item.columns = item.c == '\t' ? 1 : cell ? cell->attr.columns() : 1;
- item.x = (viscol - ((cell && m_ringview.vis_is_rtl(drow, viscol)) ? cell->attr.columns() - 1 : 0)) *
width;
+ item.x = (viscol - ((cell && bidirow->vis_is_rtl(viscol)) ? cell->attr.columns() - 1 : 0)) * width;
item.y = row_to_pixel(drow);
- item.mirror = m_ringview.vis_is_rtl(drow, viscol);
+ item.mirror = bidirow->vis_is_rtl(viscol);
item.box_mirror = (row_data && (row_data->attr.bidi_flags & VTE_BIDI_BOX_MIRROR));
if (cell && cell->c != 0) {
style = _vte_draw_get_style(cell->attr.bold(), cell->attr.italic());
@@ -9201,7 +9202,7 @@ Terminal::paint_cursor()
stem_width = (int) (((float) (m_char_ascent + m_char_descent)) *
m_cursor_aspect_ratio + 0.5);
stem_width = CLAMP (stem_width, VTE_LINE_WIDTH, m_cell_width);
- if (row_data && (row_data->attr.bidi_flags & VTE_BIDI_RTL)) // FIXME needs to use
the autodetected paragraph direction!
+ if (row_data && bidirow->base_is_rtl())
x += m_cell_width - stem_width;
_vte_draw_fill_rectangle(m_draw,
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