[cogl/wip/outputs: 45/52] Adds cogl udev api for discovering a drm device



commit 2c49774e53d38f41e0daf4f6a96784b09deda762
Author: Robert Bragg <robert linux intel com>
Date:   Thu Apr 18 17:20:04 2013 +0100

    Adds cogl udev api for discovering a drm device
    
    This adds udev based probing of drm devices that can be used by the KMS
    winsys and also support for monitoring hotplug events.

 cogl/Makefile.am                    |    5 +-
 cogl/winsys/cogl-udev-private.h     |   46 ++++++
 cogl/winsys/cogl-udev.c             |  257 +++++++++++++++++++++++++++++++
 cogl/winsys/cogl-winsys-egl-kms.c   |   43 +++---
 cogl/winsys/intel-chipset-defines.h |  287 +++++++++++++++++++++++++++++++++++
 configure.ac                        |    7 +-
 6 files changed, 618 insertions(+), 27 deletions(-)
---
diff --git a/cogl/Makefile.am b/cogl/Makefile.am
index 6d6280f..642e9c9 100644
--- a/cogl/Makefile.am
+++ b/cogl/Makefile.am
@@ -428,7 +428,10 @@ cogl_experimental_h += \
        $(srcdir)/cogl-kms-display.h
 cogl_sources_c += \
        $(srcdir)/winsys/cogl-winsys-egl-kms.c \
-       $(srcdir)/winsys/cogl-winsys-egl-kms-private.h
+       $(srcdir)/winsys/cogl-winsys-egl-kms-private.h \
+       $(srcdir)/winsys/cogl-udev.c \
+       $(srcdir)/winsys/cogl-udev-private.h \
+       $(srcdir)/winsys/intel-chipset-defines.h
 endif
 if SUPPORT_EGL_PLATFORM_XLIB
 cogl_sources_c += \
diff --git a/cogl/winsys/cogl-udev-private.h b/cogl/winsys/cogl-udev-private.h
new file mode 100644
index 0000000..ecadc2f
--- /dev/null
+++ b/cogl/winsys/cogl-udev-private.h
@@ -0,0 +1,46 @@
+/*
+ * Cogl
+ *
+ * An object oriented GL/GLES Abstraction/Utility Layer
+ *
+ * Copyright (C) 2013 Intel Corporation.
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library. If not, see
+ * <http://www.gnu.org/licenses/>.
+ *
+ */
+
+#ifndef _COGL_UDEV_DRM_PRIVATE_H_
+#define _COGL_UDEV_DRM_PRIVATE_H_
+
+typedef struct _CoglUdevDrmDevice CoglUdevDrmDevice;
+
+CoglUdevDrmDevice *
+cogl_udev_drm_device_open (CoglRenderer *renderer,
+                           CoglError **error);
+
+void
+cogl_udev_drm_device_destroy (CoglUdevDrmDevice *udev_drm_device);
+
+int
+cogl_udev_drm_device_get_fd (CoglUdevDrmDevice *udev_drm_device);
+
+typedef void (*CoglUdevDrmHotplugCallback) (void *user_data);
+
+void
+cogl_udev_drm_device_set_hotplug_callback (CoglUdevDrmDevice *udev_drm_device,
+                                           CoglUdevDrmHotplugCallback callback,
+                                           void *user_data);
+
+#endif /* _COGL_UDEV_DRM_PRIVATE_H_ */
diff --git a/cogl/winsys/cogl-udev.c b/cogl/winsys/cogl-udev.c
new file mode 100644
index 0000000..8385391
--- /dev/null
+++ b/cogl/winsys/cogl-udev.c
@@ -0,0 +1,257 @@
+/*
+ * Cogl
+ *
+ * An object oriented GL/GLES Abstraction/Utility Layer
+ *
+ * Copyright (C) 2012 Intel Corporation.
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library. If not, see
+ * <http://www.gnu.org/licenses/>.
+ */
+/**************************************************************************
+
+Copyright 1998-1999 Precision Insight, Inc., Cedar Park, Texas.
+Copyright 2001 VA Linux Systems Inc., Fremont, California.
+Copyright © 2002 by David Dawes
+Copyright © 2010 Intel Corporation
+
+All Rights Reserved.
+
+Permission is hereby granted, free of charge, to any person obtaining a
+copy of this software and associated documentation files (the "Software"),
+to deal in the Software without restriction, including without limitation
+on the rights to use, copy, modify, merge, publish, distribute, sub
+license, and/or sell copies of the Software, and to permit persons to whom
+the Software is furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice (including the next
+paragraph) shall be included in all copies or substantial portions of the
+Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+THE COPYRIGHT HOLDERS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+USE OR OTHER DEALINGS IN THE SOFTWARE.
+
+**************************************************************************/
+
+
+#include <config.h>
+
+#include "cogl-renderer-private.h"
+#include "cogl-display-private.h"
+#include "cogl-context-private.h"
+#include "cogl-framebuffer-private.h"
+#include "cogl-private.h"
+#include "cogl-error-private.h"
+#include "cogl-poll-private.h"
+
+#include "cogl-udev-private.h"
+
+#include <string.h>
+#include <stdio.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <fcntl.h>
+#include <unistd.h>
+#include <stdlib.h>
+
+#define LIBUDEV_I_KNOW_THE_API_IS_SUBJECT_TO_CHANGE
+#include <libudev.h>
+
+typedef struct _IntelChipset
+{
+  uint32_t chip_id;
+  const struct intel_device_info *info;
+  const char *name;
+} IntelChipset;
+
+struct _CoglUdevDrmDevice
+{
+  int fd;
+
+  struct udev *udev;
+  struct udev_monitor *udev_monitor;
+
+  CoglUdevDrmHotplugCallback hotplug_callback;
+  void *hotplug_user_data;
+};
+
+void
+cogl_udev_drm_device_destroy (CoglUdevDrmDevice *udev_drm_device)
+{
+  udev_monitor_unref (udev_drm_device->udev_monitor);
+  udev_unref (udev_drm_device->udev);
+
+  close (udev_drm_device->fd);
+
+  g_slice_free (CoglUdevDrmDevice, udev_drm_device);
+}
+
+static void
+handle_udev_monitor_event (void *user_data, int revents)
+{
+  CoglUdevDrmDevice *udev_drm_device = user_data;
+  struct udev_device *dev;
+  dev_t devnum;
+  struct stat st;
+  const char *hotplug;
+
+  if (!udev_drm_device->hotplug_callback)
+    return;
+
+  dev = udev_monitor_receive_device (udev_drm_device->udev_monitor);
+  if (!dev)
+    return;
+
+  devnum = udev_device_get_devnum (dev);
+  if (fstat (udev_drm_device->fd, &st) ||
+      memcmp (&st.st_rdev, &devnum, sizeof (dev_t)) != 0)
+    {
+      udev_device_unref (dev);
+      return;
+    }
+
+  hotplug = udev_device_get_property_value (dev, "HOTPLUG");
+  if (hotplug && atoi (hotplug) == 1)
+    udev_drm_device->hotplug_callback (udev_drm_device->hotplug_user_data);
+
+  udev_device_unref (dev);
+}
+
+CoglUdevDrmDevice *
+cogl_udev_drm_device_open (CoglRenderer *renderer,
+                           CoglError **error)
+{
+  struct udev *udev;
+  struct udev_enumerate *e;
+  struct udev_list_entry *entry;
+  int fd = -1;
+  struct udev_monitor *monitor;
+  CoglUdevDrmDevice *udev_drm_device;
+
+  udev = udev_new ();
+  if (udev == NULL)
+    {
+      _cogl_set_error (error,
+                       COGL_WINSYS_ERROR,
+                       COGL_WINSYS_ERROR_INIT,
+                       "Failed to init udev api");
+      return FALSE;
+    }
+
+  e = udev_enumerate_new (udev);
+  udev_enumerate_add_match_subsystem (e, "drm");
+  udev_enumerate_scan_devices (e);
+  udev_list_entry_foreach (entry, udev_enumerate_get_list_entry (e))
+    {
+      struct udev_device *udev_device =
+        udev_device_new_from_syspath (udev, udev_list_entry_get_name (entry));
+
+      /* TODO: probe device for more detailed information */
+
+      const char *path = udev_device_get_devnode (udev_device);
+      if (path)
+        {
+          fd = open (path, O_RDWR);
+          if (fd != -1)
+            {
+              udev_device_unref (udev_device);
+              break;
+            }
+          else
+            g_warning ("Failed to open device node %s: %m", path);
+        }
+      else
+        g_warning ("udev device with no corresponding devnode");
+
+      udev_device_unref (udev_device);
+    }
+
+  udev_enumerate_unref (e);
+
+  if (fd == -1)
+    {
+      udev_unref (udev);
+      _cogl_set_error (error,
+                       COGL_WINSYS_ERROR,
+                       COGL_WINSYS_ERROR_INIT,
+                       "Failed to find suitable drm device");
+      return FALSE;
+    }
+
+  monitor = udev_monitor_new_from_netlink (udev, "udev");
+  if (!monitor)
+    {
+      close (fd);
+      udev_unref (udev);
+      _cogl_set_error (error,
+                       COGL_WINSYS_ERROR,
+                       COGL_WINSYS_ERROR_INIT,
+                       "Failed to create udev monitor");
+      return FALSE;
+    }
+
+  if (udev_monitor_filter_add_match_subsystem_devtype (monitor,
+                                                       "drm",
+                                                       "drm_minor") < 0 ||
+      udev_monitor_enable_receiving (monitor) < 0)
+    {
+      udev_monitor_unref (monitor);
+      close (fd);
+      udev_unref (udev);
+      _cogl_set_error (error,
+                       COGL_WINSYS_ERROR,
+                       COGL_WINSYS_ERROR_INIT,
+                       "Failed to enable udev monitor");
+      return FALSE;
+    }
+
+  /* XXX: Note that the udev monitor has an internal pointer to udev
+   * but udev_monitor_new_from_netlink doesn't take a references on
+   * the udev object so we don't release our udev reference */
+
+  udev_drm_device = g_slice_new0 (CoglUdevDrmDevice);
+
+  udev_drm_device->fd = fd;
+  udev_drm_device->udev = udev;
+  udev_drm_device->udev_monitor = monitor;
+
+  _cogl_poll_renderer_add_fd (renderer,
+                              udev_monitor_get_fd (monitor),
+                              COGL_POLL_FD_EVENT_IN,
+                              NULL, /* no prepare function */
+                              handle_udev_monitor_event,
+                              udev_drm_device);
+
+  return udev_drm_device;
+}
+
+int
+cogl_udev_drm_device_get_fd (CoglUdevDrmDevice *udev_drm_device)
+{
+  return udev_drm_device->fd;
+}
+
+void
+cogl_udev_drm_device_set_hotplug_callback (CoglUdevDrmDevice *udev_drm_device,
+                                           CoglUdevDrmHotplugCallback callback,
+                                           void *user_data)
+{
+  udev_drm_device->hotplug_callback = callback;
+  udev_drm_device->hotplug_user_data = user_data;
+}
diff --git a/cogl/winsys/cogl-winsys-egl-kms.c b/cogl/winsys/cogl-winsys-egl-kms.c
index 2305070..c8b51c1 100644
--- a/cogl/winsys/cogl-winsys-egl-kms.c
+++ b/cogl/winsys/cogl-winsys-egl-kms.c
@@ -54,6 +54,7 @@
 #include "cogl-version.h"
 #include "cogl-error-private.h"
 #include "cogl-poll-private.h"
+#include "cogl-udev-private.h"
 
 static const CoglWinsysEGLVtable _cogl_winsys_egl_vtable;
 
@@ -61,6 +62,7 @@ static const CoglWinsysVtable *parent_vtable;
 
 typedef struct _CoglRendererKMS
 {
+  CoglUdevDrmDevice *udev_drm_device;
   int fd;
   struct gbm_device *gbm;
   CoglClosure *swap_notify_idle;
@@ -112,7 +114,14 @@ _cogl_winsys_renderer_disconnect (CoglRenderer *renderer)
   CoglRendererEGL *egl_renderer = renderer->winsys;
   CoglRendererKMS *kms_renderer = egl_renderer->platform;
 
-  eglTerminate (egl_renderer->edpy);
+  if (egl_renderer->edpy)
+    eglTerminate (egl_renderer->edpy);
+
+  if (kms_renderer->gbm)
+    gbm_device_destroy (kms_renderer->gbm);
+
+  if (kms_renderer->udev_drm_device)
+    cogl_udev_drm_device_destroy (kms_renderer->udev_drm_device);
 
   g_slice_free (CoglRendererKMS, kms_renderer);
   g_slice_free (CoglRendererEGL, egl_renderer);
@@ -272,23 +281,20 @@ _cogl_winsys_renderer_connect (CoglRenderer *renderer,
   egl_renderer->platform = g_slice_new0 (CoglRendererKMS);
   kms_renderer = egl_renderer->platform;
 
-  kms_renderer->fd = open (device_name, O_RDWR);
-  if (kms_renderer->fd < 0)
-    {
-      /* Probably permissions error */
-      _cogl_set_error (error, COGL_WINSYS_ERROR,
-                   COGL_WINSYS_ERROR_INIT,
-                   "Couldn't open %s", device_name);
-      return FALSE;
-    }
+  kms_renderer->udev_drm_device = cogl_udev_drm_device_open (renderer, error);
+  if (!kms_renderer->udev_drm_device)
+    goto error;
+
+  kms_renderer->fd =
+    cogl_udev_drm_device_get_fd (kms_renderer->udev_drm_device);
 
   kms_renderer->gbm = gbm_create_device (kms_renderer->fd);
   if (kms_renderer->gbm == NULL)
     {
       _cogl_set_error (error, COGL_WINSYS_ERROR,
-                   COGL_WINSYS_ERROR_INIT,
-                   "Couldn't create gbm device");
-      goto close_fd;
+                       COGL_WINSYS_ERROR_INIT,
+                       "Couldn't create gbm device");
+      goto error;
     }
 
   egl_renderer->edpy = eglGetDisplay ((EGLNativeDisplayType)kms_renderer->gbm);
@@ -297,11 +303,11 @@ _cogl_winsys_renderer_connect (CoglRenderer *renderer,
       _cogl_set_error (error, COGL_WINSYS_ERROR,
                    COGL_WINSYS_ERROR_INIT,
                    "Couldn't get eglDisplay");
-      goto destroy_gbm_device;
+      goto error;
     }
 
   if (!_cogl_winsys_egl_renderer_connect_common (renderer, error))
-    goto egl_terminate;
+    goto error;
 
   _cogl_poll_renderer_add_fd (renderer,
                               kms_renderer->fd,
@@ -312,12 +318,7 @@ _cogl_winsys_renderer_connect (CoglRenderer *renderer,
 
   return TRUE;
 
-egl_terminate:
-  eglTerminate (egl_renderer->edpy);
-destroy_gbm_device:
-  gbm_device_destroy (kms_renderer->gbm);
-close_fd:
-  close (kms_renderer->fd);
+error:
 
   _cogl_winsys_renderer_disconnect (renderer);
 
diff --git a/cogl/winsys/intel-chipset-defines.h b/cogl/winsys/intel-chipset-defines.h
new file mode 100644
index 0000000..5d7f599
--- /dev/null
+++ b/cogl/winsys/intel-chipset-defines.h
@@ -0,0 +1,287 @@
+#ifndef INTEL_DRIVER_H
+#define INTEL_DRIVER_H
+
+#define INTEL_VERSION 4000
+#define INTEL_NAME "intel"
+#define INTEL_DRIVER_NAME "intel"
+
+#define INTEL_VERSION_MAJOR PACKAGE_VERSION_MAJOR
+#define INTEL_VERSION_MINOR PACKAGE_VERSION_MINOR
+#define INTEL_VERSION_PATCH PACKAGE_VERSION_PATCHLEVEL
+
+#ifndef PCI_CHIP_I810
+#define PCI_CHIP_I810              0x7121
+#define PCI_CHIP_I810_DC100        0x7123
+#define PCI_CHIP_I810_E            0x7125
+#define PCI_CHIP_I815              0x1132
+#define PCI_CHIP_I810_BRIDGE       0x7120
+#define PCI_CHIP_I810_DC100_BRIDGE 0x7122
+#define PCI_CHIP_I810_E_BRIDGE     0x7124
+#define PCI_CHIP_I815_BRIDGE       0x1130
+#endif
+
+#ifndef PCI_CHIP_I830_M
+#define PCI_CHIP_I830_M            0x3577
+#define PCI_CHIP_I830_M_BRIDGE     0x3575
+#endif
+
+#ifndef PCI_CHIP_845_G
+#define PCI_CHIP_845_G            0x2562
+#define PCI_CHIP_845_G_BRIDGE     0x2560
+#endif
+
+#ifndef PCI_CHIP_I854
+#define PCI_CHIP_I854             0x358E
+#define PCI_CHIP_I854_BRIDGE      0x358C
+#endif
+
+#ifndef PCI_CHIP_I855_GM
+#define PCI_CHIP_I855_GM          0x3582
+#define PCI_CHIP_I855_GM_BRIDGE           0x3580
+#endif
+
+#ifndef PCI_CHIP_I865_G
+#define PCI_CHIP_I865_G                   0x2572
+#define PCI_CHIP_I865_G_BRIDGE    0x2570
+#endif
+
+#ifndef PCI_CHIP_I915_G
+#define PCI_CHIP_I915_G                   0x2582
+#define PCI_CHIP_I915_G_BRIDGE    0x2580
+#endif
+
+#ifndef PCI_CHIP_I915_GM
+#define PCI_CHIP_I915_GM          0x2592
+#define PCI_CHIP_I915_GM_BRIDGE           0x2590
+#endif
+
+#ifndef PCI_CHIP_E7221_G
+#define PCI_CHIP_E7221_G          0x258A
+/* Same as I915_G_BRIDGE */
+#define PCI_CHIP_E7221_G_BRIDGE           0x2580
+#endif
+
+#ifndef PCI_CHIP_I945_G
+#define PCI_CHIP_I945_G        0x2772
+#define PCI_CHIP_I945_G_BRIDGE 0x2770
+#endif
+
+#ifndef PCI_CHIP_I945_GM
+#define PCI_CHIP_I945_GM        0x27A2
+#define PCI_CHIP_I945_GM_BRIDGE 0x27A0
+#endif
+
+#ifndef PCI_CHIP_I945_GME
+#define PCI_CHIP_I945_GME       0x27AE
+#define PCI_CHIP_I945_GME_BRIDGE 0x27AC
+#endif
+
+#ifndef PCI_CHIP_PINEVIEW_M
+#define PCI_CHIP_PINEVIEW_M            0xA011
+#define PCI_CHIP_PINEVIEW_M_BRIDGE     0xA010
+#define PCI_CHIP_PINEVIEW_G            0xA001
+#define PCI_CHIP_PINEVIEW_G_BRIDGE     0xA000
+#endif
+
+#ifndef PCI_CHIP_G35_G
+#define PCI_CHIP_G35_G         0x2982
+#define PCI_CHIP_G35_G_BRIDGE  0x2980
+#endif
+
+#ifndef PCI_CHIP_I965_Q
+#define PCI_CHIP_I965_Q                0x2992
+#define PCI_CHIP_I965_Q_BRIDGE         0x2990
+#endif
+
+#ifndef PCI_CHIP_I965_G
+#define PCI_CHIP_I965_G                0x29A2
+#define PCI_CHIP_I965_G_BRIDGE         0x29A0
+#endif
+
+#ifndef PCI_CHIP_I946_GZ
+#define PCI_CHIP_I946_GZ               0x2972
+#define PCI_CHIP_I946_GZ_BRIDGE        0x2970
+#endif
+
+#ifndef PCI_CHIP_I965_GM
+#define PCI_CHIP_I965_GM        0x2A02
+#define PCI_CHIP_I965_GM_BRIDGE 0x2A00
+#endif
+
+#ifndef PCI_CHIP_I965_GME
+#define PCI_CHIP_I965_GME       0x2A12
+#define PCI_CHIP_I965_GME_BRIDGE 0x2A10
+#endif
+
+#ifndef PCI_CHIP_G33_G
+#define PCI_CHIP_G33_G         0x29C2
+#define PCI_CHIP_G33_G_BRIDGE  0x29C0
+#endif
+
+#ifndef PCI_CHIP_Q35_G
+#define PCI_CHIP_Q35_G         0x29B2
+#define PCI_CHIP_Q35_G_BRIDGE  0x29B0
+#endif
+
+#ifndef PCI_CHIP_Q33_G
+#define PCI_CHIP_Q33_G         0x29D2
+#define PCI_CHIP_Q33_G_BRIDGE  0x29D0
+#endif
+
+#ifndef PCI_CHIP_GM45_GM
+#define PCI_CHIP_GM45_GM       0x2A42
+#define PCI_CHIP_GM45_BRIDGE    0x2A40
+#endif
+
+#ifndef PCI_CHIP_G45_E_G
+#define PCI_CHIP_G45_E_G       0x2E02
+#define PCI_CHIP_G45_E_G_BRIDGE 0x2E00
+#endif
+
+#ifndef PCI_CHIP_G45_G
+#define PCI_CHIP_G45_G         0x2E22
+#define PCI_CHIP_G45_G_BRIDGE  0x2E20
+#endif
+
+#ifndef PCI_CHIP_Q45_G
+#define PCI_CHIP_Q45_G         0x2E12
+#define PCI_CHIP_Q45_G_BRIDGE  0x2E10
+#endif
+
+#ifndef PCI_CHIP_G41_G
+#define PCI_CHIP_G41_G         0x2E32
+#define PCI_CHIP_G41_G_BRIDGE  0x2E30
+#endif
+
+#ifndef PCI_CHIP_B43_G
+#define PCI_CHIP_B43_G         0x2E42
+#define PCI_CHIP_B43_G_BRIDGE  0x2E40
+#endif
+
+#ifndef PCI_CHIP_B43_G1
+#define PCI_CHIP_B43_G1                0x2E92
+#define PCI_CHIP_B43_G1_BRIDGE 0x2E90
+#endif
+
+#ifndef PCI_CHIP_IRONLAKE_D_G
+#define PCI_CHIP_IRONLAKE_D_G          0x0042
+#define PCI_CHIP_IRONLAKE_D_G_BRIDGE   0x0040
+#endif
+
+#ifndef PCI_CHIP_IRONLAKE_M_G
+#define PCI_CHIP_IRONLAKE_M_G          0x0046
+#define PCI_CHIP_IRONLAKE_M_G_BRIDGE   0x0044
+#endif
+
+#ifndef PCI_CHIP_SANDYBRIDGE_BRIDGE
+#define PCI_CHIP_SANDYBRIDGE_BRIDGE    0x0100  /* Desktop */
+#define PCI_CHIP_SANDYBRIDGE_GT1       0x0102
+#define PCI_CHIP_SANDYBRIDGE_GT2       0x0112
+#define PCI_CHIP_SANDYBRIDGE_GT2_PLUS  0x0122
+#define PCI_CHIP_SANDYBRIDGE_BRIDGE_M  0x0104  /* Mobile */
+#define PCI_CHIP_SANDYBRIDGE_M_GT1     0x0106
+#define PCI_CHIP_SANDYBRIDGE_M_GT2     0x0116
+#define PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS        0x0126
+#define PCI_CHIP_SANDYBRIDGE_BRIDGE_S  0x0108  /* Server */
+#define PCI_CHIP_SANDYBRIDGE_S_GT      0x010A
+
+#define PCI_CHIP_IVYBRIDGE_M_GT1       0x0156
+#define PCI_CHIP_IVYBRIDGE_M_GT2       0x0166
+#define PCI_CHIP_IVYBRIDGE_D_GT1       0x0152
+#define PCI_CHIP_IVYBRIDGE_D_GT2       0x0162
+#define PCI_CHIP_IVYBRIDGE_S_GT1       0x015a
+#define PCI_CHIP_IVYBRIDGE_S_GT2       0x016a
+
+#define PCI_CHIP_HASWELL_D_GT1         0x0402
+#define PCI_CHIP_HASWELL_D_GT2         0x0412
+#define PCI_CHIP_HASWELL_D_GT2_PLUS    0x0422
+#define PCI_CHIP_HASWELL_M_GT1         0x0406
+#define PCI_CHIP_HASWELL_M_GT2         0x0416
+#define PCI_CHIP_HASWELL_M_GT2_PLUS    0x0426
+#define PCI_CHIP_HASWELL_S_GT1         0x040A
+#define PCI_CHIP_HASWELL_S_GT2         0x041A
+#define PCI_CHIP_HASWELL_S_GT2_PLUS    0x042A
+#define PCI_CHIP_HASWELL_SDV_D_GT1     0x0C02
+#define PCI_CHIP_HASWELL_SDV_D_GT2     0x0C12
+#define PCI_CHIP_HASWELL_SDV_D_GT2_PLUS        0x0C22
+#define PCI_CHIP_HASWELL_SDV_M_GT1     0x0C06
+#define PCI_CHIP_HASWELL_SDV_M_GT2     0x0C16
+#define PCI_CHIP_HASWELL_SDV_M_GT2_PLUS        0x0C26
+#define PCI_CHIP_HASWELL_SDV_S_GT1     0x0C0A
+#define PCI_CHIP_HASWELL_SDV_S_GT2     0x0C1A
+#define PCI_CHIP_HASWELL_SDV_S_GT2_PLUS        0x0C2A
+#define PCI_CHIP_HASWELL_ULT_D_GT1     0x0A02
+#define PCI_CHIP_HASWELL_ULT_D_GT2     0x0A12
+#define PCI_CHIP_HASWELL_ULT_D_GT2_PLUS        0x0A22
+#define PCI_CHIP_HASWELL_ULT_M_GT1     0x0A06
+#define PCI_CHIP_HASWELL_ULT_M_GT2     0x0A16
+#define PCI_CHIP_HASWELL_ULT_M_GT2_PLUS        0x0A26
+#define PCI_CHIP_HASWELL_ULT_S_GT1     0x0A0A
+#define PCI_CHIP_HASWELL_ULT_S_GT2     0x0A1A
+#define PCI_CHIP_HASWELL_ULT_S_GT2_PLUS        0x0A2A
+#define PCI_CHIP_HASWELL_CRW_D_GT1     0x0D12
+#define PCI_CHIP_HASWELL_CRW_D_GT2     0x0D22
+#define PCI_CHIP_HASWELL_CRW_D_GT2_PLUS        0x0D32
+#define PCI_CHIP_HASWELL_CRW_M_GT1     0x0D16
+#define PCI_CHIP_HASWELL_CRW_M_GT2     0x0D26
+#define PCI_CHIP_HASWELL_CRW_M_GT2_PLUS        0x0D36
+#define PCI_CHIP_HASWELL_CRW_S_GT1     0x0D1A
+#define PCI_CHIP_HASWELL_CRW_S_GT2     0x0D2A
+#define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS        0x0D3A
+
+#define PCI_CHIP_VALLEYVIEW_PO         0x0f30
+
+#endif
+
+#define I85X_CAPID                     0x44
+#define I85X_VARIANT_MASK                      0x7
+#define I85X_VARIANT_SHIFT                     5
+#define I855_GME                               0x0
+#define I855_GM                                        0x4
+#define I852_GME                               0x2
+#define I852_GM                                        0x5
+
+#define I810_MEMBASE(p,n) (p)->regions[(n)].base_addr
+#define VENDOR_ID(p)      (p)->vendor_id
+#define DEVICE_ID(p)      (p)->device_id
+#define SUBVENDOR_ID(p)          (p)->subvendor_id
+#define SUBSYS_ID(p)      (p)->subdevice_id
+#define CHIP_REVISION(p)  (p)->revision
+
+#define INTEL_INFO(intel) ((intel)->info)
+#define IS_GENx(intel, X) (INTEL_INFO(intel)->gen >= 10*(X) && INTEL_INFO(intel)->gen < 10*((X)+1))
+#define IS_GEN1(intel) IS_GENx(intel, 1)
+#define IS_GEN2(intel) IS_GENx(intel, 2)
+#define IS_GEN3(intel) IS_GENx(intel, 3)
+#define IS_GEN4(intel) IS_GENx(intel, 4)
+#define IS_GEN5(intel) IS_GENx(intel, 5)
+#define IS_GEN6(intel) IS_GENx(intel, 6)
+#define IS_GEN7(intel) IS_GENx(intel, 7)
+#define IS_HSW(intel) (INTEL_INFO(intel)->gen == 75)
+
+/* Some chips have specific errata (or limits) that we need to workaround. */
+#define IS_I830(intel) (DEVICE_ID((intel)->PciInfo) == PCI_CHIP_I830_M)
+#define IS_845G(intel) (DEVICE_ID((intel)->PciInfo) == PCI_CHIP_845_G)
+#define IS_I865G(intel) (DEVICE_ID((intel)->PciInfo) == PCI_CHIP_I865_G)
+
+#define IS_I915G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I915_G || DEVICE_ID(pI810->PciInfo) == 
PCI_CHIP_E7221_G)
+#define IS_I915GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I915_GM)
+
+#define IS_965_Q(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_Q)
+
+/* supports Y tiled surfaces (pre-965 Mesa isn't ready yet) */
+#define SUPPORTS_YTILING(pI810) (INTEL_INFO(intel)->gen >= 40)
+#define HAS_BLT(pI810) (INTEL_INFO(intel)->gen >= 60)
+
+struct intel_device_info {
+       int gen;
+};
+
+#if 0
+void intel_detect_chipset(ScrnInfoPtr scrn,
+                         EntityInfoPtr ent,
+                         struct pci_device *pci);
+#endif
+
+
+#endif /* INTEL_DRIVER_H */
diff --git a/configure.ac b/configure.ac
index 5d7e415..7f4d9f6 100644
--- a/configure.ac
+++ b/configure.ac
@@ -1076,11 +1076,7 @@ AS_IF([test "x$enable_kms_egl_platform" = "xyes"],
         NEED_EGL=yes
         EGL_PLATFORMS="$EGL_PLATFORMS kms"
 
-        PKG_CHECK_EXISTS([gbm],
-                         [
-                           COGL_PKG_REQUIRES="$COGL_PKG_REQUIRES gbm"
-                           COGL_PKG_REQUIRES="$COGL_PKG_REQUIRES libdrm"
-                         ],
+        PKG_CHECK_EXISTS([gbm], [],
                          [AC_MSG_ERROR([Unable to locate required kms libraries])])
 
         GBM_VERSION=`$PKG_CONFIG --modversion gbm`
@@ -1092,6 +1088,7 @@ AS_IF([test "x$enable_kms_egl_platform" = "xyes"],
         AC_DEFINE_UNQUOTED([COGL_GBM_MINOR], [$GBM_MINOR], [The minor version for libgbm])
         AC_DEFINE_UNQUOTED([COGL_GBM_MICRO], [$GBM_MICRO], [The micro version for libgbm])
 
+        COGL_PKG_REQUIRES="$COGL_PKG_REQUIRES gbm libdrm libudev pciaccess"
         COGL_DEFINES_SYMBOLS="$COGL_DEFINES_SYMBOLS COGL_HAS_EGL_PLATFORM_KMS_SUPPORT"
 
         VTS_PKG_REQUIRES="libsystemd-daemon libsystemd-journal libsystemd-login libudev libdrm"


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