trouble with make


This is the content of my Makefile:
CC == gcc
arrow : arrow.c
      $(CC) `gtk-config --cflags` arrow.c -o arrow `gtk-config --libs`

      rm -f *.o arrow

arrow.c is the name of my source file.

when i type "make" and hit enter to i get the ***No target . stop"...or when i type "make arrow".. or "make a.out"
.. i get the error "not rule to make target `a.out',....

what is the correct synatx for the make command?.
I do:
make clean
make install
make arrow

does not want to work.


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